На плате имеется микросхема с маркировкой PO86A RC5057M A2. Согласно даташиту:
Pin Definitions
1 ENABLE/SS
Output Enable/Softstart.
A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start.
2 PWRGD
Power Good Flag.
An open collector output that will be logic LOW if the output
voltage is not within ±12% of the nominal output voltage setpoint.
3 IFB
Current Feedback.
Pin 3 is used in conjunction with pin 10, as the input for the
current feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details.
4 VFB
Voltage Feedback.
Pin 4 is used as the input for the voltage feedback control
loop. See Application Information for details regarding correct layout.
5 VCCA
Analog VCC.
Connect to system 5V supply and decouple with a 0.1μF ceramic
capacitor.
6 GNDP
Power Ground.
Return pin for high currents flowing in pin 8 (VCCP). Connect to
a low impedance ground.
7 LODRV
Low Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET for
synchronous operation. The trace from this pin to the MOSFET gate should be <0.5".
8 VCCP
Power VCC.
For both high side and low side FET drivers. Connect to system 12V
supply, and decouple with a 4.7μF tantalum and a 0.1μF ceramic capacitor.
9 HIDRV
High Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should be <0.5".
10 SW
High side driver source and low side driver drain switching node.
Together
with IFB pin allows FET sensing for current.
11 GNDA
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
12–16 VID0-4
Voltage Identification Code Inputs.
These open collector/TTL compatible inputs
will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.
На плате имеется микросхема с маркировкой PO86A RC5057M A2. Согласно даташиту:
Pin Definitions
1 ENABLE/SS
Output Enable/Softstart.
A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start.
2 PWRGD
Power Good Flag.
An open collector output that will be logic LOW if the output
voltage is not within ±12% of the nominal output voltage setpoint.
3 IFB
Current Feedback.
Pin 3 is used in conjunction with pin 10, as the input for the
current feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details.
4 VFB
Voltage Feedback.
Pin 4 is used as the input for the voltage feedback control
loop. See Application Information for details regarding correct layout.
5 VCCA
Analog VCC.
Connect to system 5V supply and decouple with a 0.1μF ceramic
capacitor.
6 GNDP
Power Ground.
Return pin for high currents flowing in pin 8 (VCCP). Connect to
a low impedance ground.
7 LODRV
Low Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET for
synchronous operation. The trace from this pin to the MOSFET gate should be <0.5".
8 VCCP
Power VCC.
For both high side and low side FET drivers. Connect to system 12V
supply, and decouple with a 4.7μF tantalum and a 0.1μF ceramic capacitor.
9 HIDRV
High Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should be <0.5".
10 SW
High side driver source and low side driver drain switching node.
Together
with IFB pin allows FET sensing for current.
11 GNDA
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
12–16 VID0-4
Voltage Identification Code Inputs.
These open collector/TTL compatible inputs
will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.
VID4 VID3 VID2 VID1 VID0 NominalVOUT
0 1 1 1 1 1.30V
0 1 1 1 0 1.35V
0 1 1 0 1 1.40V
0 1 1 0 0 1.45V
0 1 0 1 1 1.50V
0 1 0 1 0 1.55V
0 1 0 0 1 1.60V
0 1 0 0 0 1.65V
0 0 1 1 1 1.70V
0 0 1 1 0 1.75V
0 0 1 0 1 1.80V
0 0 1 0 0 1.85V
0 0 0 1 1 1.90V
Note:
1. 0 = processor pin is tied to GND.
1 = processor pin is open.
Подскажите, пожалуйста, как проверить установленную конфигурацию VID. Из инструментов только тестер.
Сам даташит: alldatasheet.com/datasheet-pdf/pdf/82527/FAIRCHILD/RC5057M.html